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Cadence Design Entry HDL15.5原理圖設(shè)計(jì)英文原版教程

（內(nèi)部原版培訓(xùn)教程 ￥80）

         Design Entry HDL 是Cadence原理圖輸入工具，該套教程是Cadence公司推出的關(guān)于Design Entry HDL使用培訓(xùn)的內(nèi)部培訓(xùn)教材，共9個(gè)Lesson，342頁(yè)；詳細(xì)講解了Design Entry HDL 電路原理圖設(shè)計(jì)的概念、流程、和Symbol庫(kù)文件的具體使用操作。是Cadence原理圖設(shè)計(jì)的入門(mén)和提高最經(jīng)典教程；教程內(nèi)容簡(jiǎn)介如下：

        Lesson 1: Getting Started
        This first lesson will cover the design flow that is used in the course as well as an introduction to the tools that are used in the flow. This lesson will give lab instructions and a reference schematic; you will build a new project and create both flat and hierarchical schematics. You will also use other related tools common to themainstream board design flow.

        Lesson 2: Design Entry
        You will learn how to create a new schematic design, and learn about project setup and file structure. This lesson will also cover design checking and cross referencing netnames from one sheet to another.

        Lesson 3: Part Tables
        This lesson shows you how to add capacitors to the design by selecting them from a property table.

        Lesson 4: Packaging
        The objective of the following lesson is to show you the intricacies of the Packager XL tool and how you can affect the component assignments by the use of manual and property assignments. The lesson will also cover the creation of Bills of Materials and using the output from the Packager XL tool to create netlist reports.

        Lesson 5: Introduction to Board Layout
        This lesson will instruct you in using the Packager XL tool to transfer design data contained in the schematic to the PCB Editor tool. It also covers using the Design Differences tool to compare the schematic database to the board database.

        Lesson 6: Hierarchical Design
        This lesson acquaints you with the structure of hierarchical schematics within the DE HDL tool. The lesson covers the basics of creating a hierarchical schematic, including how connectivity is handled for hierarchical designs, plotting a hierarchical schematic, and the use of the Variant Editor tool to create variant Bills of Materials and variant schematics.

        Lesson 7: Design Rules
        This lesson shows you how to use properties that affect part placement and signal routing in PCB Editor. This lesson also provides an introduction to the Constraint Manager and the use of the Routing Workbook. For a more detailed look at the Constraint Manager and the Signal Integrity and Timing Workbooks, please see the Allegro PCB SI Foundations course.

        Lesson 8: Transfer to PCB Editor
        You will now transfer the hierarchical design to PCB Editor, place parts and route signals. This lesson also shows you how to compare the DE HDL schematic to the PCB Editor board, how to resolve differences by backannotating the DE HDL schematic, and how to archive the project.

        Lesson 9: Engineering Changes
        This lesson is designed to instruct you in the process and commands used to make modifications to the schematic design and then incorporate those modifications into the PCB Editor database.

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