[CST - PCB] Weird frequency shift of the frequency response of a filter

Hello everyone,
I have designed a filter with lumped element in CST (central frequency is 400 MHz). They have been modeled with their S-parameters. By means of a S-parameters task, I have obtained the frequency response (S21 parameter).
Then, I have realized the PCB of filter and, by means of PEEC method, I performed a new S-parameter task simulation to obtain the frequency response of filter taking into account the PCB effects. The frequency response obtained with PEEC has the same shape of the previous one, but it is shifted to left of about 35 MHz.
What does it mean? Is it an error about how I set the PEEC simulations or about how the PCB has been designed? I don't know how to explain to myself this result.
Many thanks in advance.
Regards,
Antonio L.

Maybe you can do some yield analysis.
Every lumped element has some tolerance, such as 100pF with 20% tolerance.
That is common phenomenan that the filter center freq drift.
Another point is that you can't use the element S-params, which has less precision.
For low freq, such as your case, maybe other simulation, such as spice, has more precison than S-params.
Good luck.
Tony Liu

Maybe I misunderstand the question, but when you go from schematic with SMD data to real layout, adding connections, the additional length from lines adds inductance. That can shift your frequency down. Same for SMD pads, if they are not yet included in the SMD S2P data.

I have not modeled the inductance of the lines in the schematic because, I thought, the frequency range is low (about 400 MHz). The parisitic inductance should have been neglectable at that frequency. I would have never thought about it
What is the parasitic parameter due to SMD pads? Capacitance or inductance?
Many thanks.
Regard,
Antonio

for starters, just calculate the parallel plate capacitance using C = e0* er* L * W/D